Project title: High-Performance Wrap-Gated III-V Nanowire Parallel Array MOSFETs on Silicon 

In the past few decades, semiconductor device scaling has been the major driving force for technology advancements in the electronics industry. In order to sustain these scaling needs, as predicted by the 2011 International Technology Roadmap for Semiconductors (ITRS), non-planar device nanostructures (e.g. nanowires) as well as III-V materials will soon be integrated with conventional silicon technology to provide performance enhancements including the larger field-effect mobility and better gate electrostatic to deliver higher drive currents. For example, the first wrap-gated III-V MOSFETs with a high-mobility In0.53Ga0.47As nanowire parallel array channel have been recently demonstrated for their superior electrical performances and effective control in suppressing the short channel effect. Still, there are several key issues that need to be resolved before manufacturing III-V nanowire-based commercial electronic products. The major challenge is to integrate nanowire transistors with stable device characteristics and low intrinsic noise. However, due to the extraordinarily large surface-area-to-volume ratio and reactive crystal surfaces of III-V nanowires as compared to state-of-the-art Si structures, the electronic properties of nanowire devices are extremely sensitive to the nanowire surface and/or interface traps existed between the nanowire channel and gate dielectric, especially for the wrap-gated nanowire devices. As a result, it is extremely important but challenging to control these defect states and to develop methods to quantify their impact on the device characteristics and stabilities. In this proposal, we will utilize the low-frequency noise measurement which is a very sensitive characterization of the quality and reliability of electronic devices. By employing crystalline InAs, GaAs and InGaAs nanowires as the representative binary and ternary high-mobility III-V nanowire materials assembled on silicon, the aim is to develop wrap-gated nanowire parallel array MOSFETs and to further enhance the device performances and stabilities through a series of well-designed and systematic noise studies ranging from the optimization of high- dielectrics, consideration of nanowire dimensions, to the selection of gate electrodes. Ultimately, we will extend this work to establish a versatile and powerful technology platform to establish design guidelines for the optimized nanowire device performance enhancement for future electronics through the complementary I-V and noise characterization. 

Supervisor: Dr Johnny C. Ho (

Suitable for: M.Phil./Ph. D