Project title: Fundamental Properties and Performance Limits of Parallel Arrays of III-V Nanowires for Integrated Circuits


Synthetic nanomaterials, such as semiconductor nanowires (NW) will play an essential role in the future of integrated circuits due to the unique electrical and physical properties arising from their qusai one-dimensional (1-D) structure. Through integration with conventional silicon (Si) technology, they enable further miniaturization of devices, enhance switching speed, and reduce power consumption as compared to conventional planar structures. However, many challenges still remain in controlling the synthesis and assembly, understanding the fundamental properties, detailed device characterization, and establishing the performance limits of the integrated circuits based on these synthetic nanostructures. In this proposal, we will emphasize on III-V NWs which have been shown to exhibit high carrier mobility and low off-state leakage. The aim is to address these challenges through a series of well-designed and systematic experiments ranging from NW synthesis to circuit integration studies. Ultimately, we will extend this work to parallel NW arrays assembled on plastic substrates, thereby utilizing high performance crystalline inorganic nanomaterials for low-cost, large-scale, and flexible electronics.


Supervisor: Dr Johnny C. Ho (johnnyho@cityu.edu.hk)


Suitable for: M.Phil./Ph. D